product description 1 eds-103162 rev c 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for i naccuracies or omissions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user?s own risk. prices and specifications are subject to chang e without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third p arty. sirenza microdevices does not authorize or warrant any sirenza microdevices product for use in lif e-support devices and/or systems. copyright 2006 sirenza microdevices, inc. all worldwide rights reserved. 0 5 10 15 20 25 30 35 40 0246810 5v 40ma 3v 20ma SPF-3143Z low noise phemt gaas fet product features ? available in lead free, rohs compliant, & green packaging ? dc-3.5 ghz operation ? 0.58 db nf min @ 2 ghz ? 21 db g max @ 2 ghz ? +31 dbm oip3 (5v,40ma) ? +17.7 dbm p1db (5v,40ma) ? low current, low cost ? apps circuits available for key bands applications ? analog and digital wireless systems ? 3g, cellular, pcs ? fixed wireless, pager systems ? driver stage for low power applications sirenza microdevices? SPF-3143Z is a high performance 0.5 m phemt gallium arsenide fet. this 600 m device is ideally biased at 3v, 20ma for lowest noise performance and battery powered requirements. at 5v, 40ma the device can deliver oip3 of 32.5 dbm. it provides ideal performance as a driver stage in many commercial and industrial lna applications. the matte tin finish on sirenza?s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is rohs compliant per eu directive 2002/95. this package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retardants. typical gain performance frequency (ghz) gain, gmax (db) gmax gain pb rohs compliant & package green symbol parameters test conditions v ds =5v, i dq =40ma, 25c (unless otherwise noted) units test frequency (ghz) min. typ. max. 0.9 23.3 1.9 19.9 0.9 0.36 1.9 0.58 s 21 insertion gain z s =z l =50 db 0.9 18.2 19.7 21.2 nf noise figure application circuit db 1.9 0.8 1.0 gain gain application circuit db 1.9 14.1 15.6 17.1 oip 3 output third order intercept point application circuit, tone spacing = 1mhz, pout p er tone = 0 dbm dbm 1.9 30.5 32.5 p 1db output power at 1db compression application circuit 1.9 19.0 20.5 v p pinchoff voltage v ds = 2v, i ds = 0.6ma v -1.4 -1.0 -0.6 i dss saturated drain current v ds = 2v, v gs = 0 v ma 180 g m transconductance v ds = 2v, v gs = 0 v ms 210 bvgso gate-source breakdown voltage i gs = 300 a, drain open v -10 -7 bvgdo gate-drain breakdown voltage i gd = 300 a, source open v-12-7 v ds device operating voltage drain-source v 5.5 i ds device operating current drain-source ma 38 40 42 r th , j-l thermal resistance (junction - lead) junction to lead c/w 200 db g max maximum available gain z s =z s *, z l =z l * db nf min minimum noise figure z s = opt , z l =z l *
SPF-3143Z low noise phemt gaas fet 2 eds-103162 rev c 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com absolute maximum ratings q e r f ) z h g ( v s d ) v ( i q d ) a m ( f n n i m ] 1 [ ) b d ( x a m g ) b d ( b d 1 p ] 2 [ ) m b d ( 3 p i o ] 3 [ ) m b d ( 0 9 . 0 30 25 2 . 05 . 1 25 19 2 50 46 3 . 03 . 3 28 11 3 0 9 . 1 30 20 5 . 03 . 8 15 19 2 50 48 5 . 01 . 9 18 11 3 [1] z s = opt , z l =z l *, the input matching circuit losses have been de-emebedded. [2] z s =z sopt , z l =z lopt , where z sopt and z lopt have been tuned for max p1db [3] z s =z sopt , z l =z lopt , where z sopt and z lopt have been tuned for max oip3 note: optimum nf, p1db, and oip3 performance cannot be achieved simultaneously. peak rf performance under optimum matching conditions s g d z sopt z lopt biasing details the SPF-3143Z is a depletion mode fet and requires a negative gate voltage to achieve pinchoff. as such, power supply sequencing circuitry is strongly recommended to prevent damaging bias transients during turn-on. active bias circuitry is also recommended to maintain a constant drain current from part-to-part. junction temperature calculation mttf is inversely proportional to the device junction temperature. for junction temperature and mttf consid- erations the device operating conditions should also satisfy the following expression: p dc < (t j - t l ) / r th where: p dc = i ds * v ds (w) t j = junction temperature (c) t l = lead temperature (pin 2) (c) r th = thermal resistance (c/w) r e t e m a r a p l o b m y s e u l a v t i n u t n e r r u c n i a r di s s d 0 8 1a m t n e r r u c e t a g d r a w r o fi f s g 0 0 6a t n e r r u c e t a g e s r e v e ri r s g 0 0 6a e g a t l o v e c r u o s - o t - n i a r dv s d 7v e g a t l o v e c r u o s - o t - e t a gv s g 0 > r o 3 - SPF-3143Z low noise phemt gaas fet 3 eds-103162 rev c 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com l c 5. die is facing up for mold and facing down l c 6. package surface to be mirror finish. for trim/form. ie :reverse trim/form. 4. all specifications comply to eiaj sc70. 2. dimensions are inclusive of plating. 3. dimensions are exclusive of mold flash 1. all dimensions are in millimeters. & metal burr. note: d e he a2 e e b b1 l c q1 a a1 package dimensions f31z use multiple plated-through vias holes located close to the package pins to ensure a good rf ground connection to a continuous groundplane on the backside of the board. recommended pcb layout sot-343 package plated thru holes (0.020" dia) ground plane 1 4 2 3 pin designation # n i p n o i t c n u f n o i t p i r c s e d 1e t a gs a i b e t a g / t u p n i f r 2e c r u o sd a e l e c u d e r o t s e l o h a i v e s u . d n u o r g o t n o i t c e n n o c . e l b i s s o p s a s d a e l d n u o r g o t e s o l c s a s a i v e c a l p . e c n a t c u d n i 3n i a r ds a i b n i a r d / t u p t u o f r 4e c r u o sn i p g n i d n u o r g d n e m m o c e r / n o i t c e n n o c o n pin description r e b m u n t r a p e z i s l e e r l e e r / s e c i v e d z 3 4 1 3 - f p s" 70 0 0 3 part number ordering information the part will be symbolized with the ?f31z? designator and a dot signifying pin 1 on the top surface of the package. part symbolization l o b m y sm o n e5 2 . 1 d5 0 . 2 e h0 1 . 2 a5 0 . 1 2 a0 9 . 0 1 a5 0 . 0 1 q5 2 . 0 e5 6 . 0 b5 7 3 . 0 1 b5 7 6 . 0 c4 1 . 0 l0 2 . 0
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